This invention relates generally to video graphics circuitry and more particularly to parallel processing of pixel information.
Video graphics circuitry is used in a plurality of applications such as computers, video games, and televisions. Such video graphics circuits process images for subsequent display, where a plurality of object-elements form each of the images. The object-elements are polygon shapes and, in most applications, are triangles. By reducing the image to a plurality of triangles, the data that needs to be stored and processed is simplified.
For each triangle of an image, vertex information or vertex parameters are maintained. The vertex parameters include for each vertex of the triangle, a physical location (i.e., the physical pixel location on a display), color information (e.g., RGB values), texture mapping information, and/or Z buffer information (e.g., the depth at which the image is to be perceived when displayed).
When a video graphics circuit receives the vertex parameters, it converts them to object-element information, which is used by an edgewalker circuit to facilitate walking edges of the triangle. Having identified an edge of a triangle, the video graphics circuitry spans along a horizontal line of the triangle. The spanning is done by a pixel by pixel basis wherein pixel information is generated for each pixel that is spanned. The pixel information includes color information, Z buffer information, texture information, etc.
In such video graphics circuits, pixel information is generated in a serial fashion. To enhance the serial processing of pixel information, pipelines are used, but the pixel information is still generated in serial. As is generally known in the art, data processing may be improved by processing the data in a parallel manner. This concept has been applied to video graphics circuits. Such parallel processing video graphics circuits have done the parallel processing at the triangle level or at the span level. In a video graphics circuit that parallel processes at the triangle level, the circuit includes two similar pipelined circuits, such as the ones described above. Thus, the efficiency obtained with parallel triangle processing is obtained by doubling the hardware of the circuit.
Parallel span processing video graphics circuits process span lines in parallel. Span parallel processing requires almost a doubling of the pipeline pixel processing circuitry. As such, a parallel edgewalker circuit and subsequent circuitry is needed to generate the pixel information and achieve the benefits of parallel processing.
In both the span parallel processing and the triangle parallel processing video graphics circuits, additional circuitry is needed to ensure that the parallel processing is done efficiently and without corruption of the data. Even though additional circuitry is added to ensure efficiency, efficiency may not always be optimized. For example, if multiple triangles are being simultaneously rendered in parallel, the efficiency will be optimized when the triangles are of substantially equal size. When the size difference between the triangles becomes substantial, the efficiency of the parallel processing decreases. The additional circuitry also monitors each parallel pipeline to ensure that they are processing relevant parallel data (i.e., to avoid race conditions and corruption of the data).
Therefore, a need exists for a method and apparatus that allows parallel processing within a video graphics circuit that, in many instances, is more efficient and require less hardware than span and triangle parallel processing video graphics circuits.